In conventional lithographic processing, integrated circuits are created by exposing a pattern of features contained on a mask or reticle onto a wafer that is coated with light sensitive materials. After exposure, the wafer is then chemically and mechanically processed to create the circuit elements corresponding to the features on the wafer. The process is then repeated for the next layer of the integrated circuit in order to build up the circuit on a layer by layer basis.
The ability of a photolithographic imaging system to accurately print a desired pattern of features on a wafer is diminished as the size and/or spacing of the features becomes smaller and smaller. Optical and other process distortions occur such that the way in which small or very closely spaced features are printed on the wafer may vary substantially from a desired target pattern. To compensate for these distortions, numerous resolution enhancement techniques (RETs) such as optical and process correction (OPC), sub-resolution assist features (SRAFs), phase shifting masks (PSMs) and others have been developed that increase the fidelity with which a target pattern of features can be printed on a wafer.
One technique that can also be used to print small and/or densely packed features is called double patterning. With double patterning, a target pattern of features to be printed on a wafer is divided among two or more masks. Each mask generally prints every other feature of the target pattern on the wafer. The features of the second mask are positioned to be printed in the spaces that are between the features printed by the first mask. Because the features on each mask are spaced farther apart, they are not distorted as much during the printing process.
Double patterning techniques are one of many multiple mask processing approaches that assemble the final pattern using multiple exposures. As commonly used, the term “double exposure” refers to the use of two photomasks to expose the same photoresist, which is then processed only after all exposures are made. Some applied phase-shifting mask techniques well known in the art use double exposure, in which certain high resolution features are provided by one mask, while other lower resolution features are provided by another mask. The separation of layouts for use with double-dipole lithography, in which layouts are parsed into horizontally and vertically oriented portions for exposure with vertical and horizontally oriented dipole illumination, respectively, is another example of a double exposure technique.
In what is commonly called “double patterning”, the layout is again parsed between two photomasks, but the process is usually designed such that, after the initial exposure with one mask, the wafer is processed and the patterns fixed, typically using an intermediate hard mask on the wafer. The wafer is then recoated with photoresist for exposure to the second photomask, followed with a second sequence of processing steps to produce the final pattern. Since the initial layout is processed and preserved for later use in the second patterning step, there is more flexibility in the layout parsing rules and processing conditions under which double patterning can be carried out.
Despite the benefits that may be obtained with the double patterning process, the technique can be difficult to implement with real world lithographic designs. In particular, it can be difficult and time consuming to separate a target pattern of features into two or more mask layouts in a way that ensures that each mask does not have features that are spaced within a predetermined distance of each other. Therefore, there is a need for a more efficient technique for preparing mask layouts for use with a double patterning photolithographic process.